How Broadcom Interviews in 2026: Process, Questions & What They Score
The complete process, reported questions, and what interviewers score.
Broadcom / Interview snapshot
8
stages from
application to offer
35
reported questions
31
public sources
Independent: SupaCV is not affiliated with or endorsed by Broadcom. This is one well-documented shape of Broadcom's interviews, not a script: processes change and vary by role, team, level, and region, so confirm specifics with your recruiter.
On this page
01 / For every Broadcom candidate
The process, start to finish.
Broadcom's process varies by business unit and region; Blind posts name groups such as CSG, DCSG (data center solutions group), Brocade, a PCIe switch group and VCF (VMware). This playbook covers the semiconductor engineering track the company is best known for: ASIC/RTL design, verification, firmware/embedded, and the C-heavy systems software that ships with its chips. VMware software roles are noted only where they differ (more virtualization, cloud, and LeetCode-plus-system-design content).
The shape described by prep sites and a few candidates is a recruiter screen, a hiring manager screen, a technical phone screen, then a long onsite or virtual loop (Blind posts mention scheduled loops of 5 to 7 hours; prep sites say 3 to 6 rounds) with engineers plus a manager or director, sometimes followed by an HR discussion.
Stage lists differ between sources, and early-career routes look shorter: a Plano intern reported one Zoom interview mixing technical and behavioral questions, and an intern-focused guide lists a recruiter screen and one or two technical interviews. A November 2025 India report on Taro describes two technical rounds, a manager round and an HR discussion.
Several reports mention basic C and bit manipulation in firmware and networking software interviews, and one 2019 Blind post says interviewers pressed for details of the candidate's current project. No published Broadcom interview process or evaluation framework was found, so no framework is included.
Public evidence is thin: Glassdoor, LeetCode Discuss, AmbitionBox and Dataford are not among the sources, so firsthand reports here come from Taro and Blind (many Blind items are previews or candidates asking what to expect), and the hardware-specific question lists come mostly from commercial prep sites that do not cite candidate sources.
Stage 1: Application or referral
varies
Through the Broadcom careers site (a Workday portal per one intern guide), referrals, campus hiring, recruiters, LinkedIn or job boards. One Blind poster was approached by a recruiter from an external firm (Inmeta) for an ASIC design role, and a Broadcom employee advised going through that recruiter. Time to first contact varies by business unit and region.
Stage 2: Recruiter screen
about 30 minutes per two prep sites
Background, interest in the division, role alignment and compensation expectations. TechPrep and CleverPrep (ASIC page) state 30 minutes; an intern-focused guide says 15 to 30 minutes; the other cited pages and the candidate reports give no length.
Stage 3: Hiring manager screen
30 to 45 minutes per one prep site
TechPrep describes a mix of fit and high-level technical questions about past projects. Only TechPrep states the 30 to 45 minute length; TechInterview lists the stage without a length. One Blind candidate for a senior software role in VCF cleared a hiring manager round before the loop (2025); a former employee being recruited back reported two phone interviews, with a director and a lead, that insisted on details of the current project (2019). Not every route has this stage: CleverPrep and Hyring list no separate hiring manager screen.
Listed by TechPrep, TechInterview and two Blind posts; absent from CleverPrep, Hyring and the intern route
Stage 4: Technical phone screen
60 to 90 minutes per prep sites; one Blind poster was scheduled for 45 minutes
With an engineer on the team. Software and firmware candidates report coding plus technical discussion, mostly C and some bit manipulation; hardware candidates get digital design, Verilog/SystemVerilog and timing fundamentals per prep sites. TechPrep and TechInterview state 60 to 90 minutes and CleverPrep (ASIC) states 60; the 45 minute figure comes from an April 2024 Blind poster who said a recruiter had set up a 45 minute initial interview with an engineer, not from a completed-interview report.
Stage 5: Assessment or RTL design exercise
variesSome routes only
Some routes include an online test, take-home, or live exercise. One prep site describes a 3 to 5 hour RTL exercise for ASIC design, but no firsthand report cited here confirms it. Hyring lists generic assessment formats (aptitude test, case, role task, assignment) that do not look engineering-specific, and an intern guide says no standardized online assessment has been documented for interns. Whether it happens varies by team, level and campus versus lateral hiring.
Prep-site claim only; not confirmed by a candidate report
Stage 6: Onsite or virtual loop
5 to 7 hours in Blind posts
Blind posts mention a 7 hour full-day onsite for an ASIC design role (2023; the poster was scheduled for it and asked what to expect), a 7 hour (9 to 5) onsite for a firmware MAC system team (2018; the poster asked what to prepare), and a 5 hour final loop for a senior software role in VCF with three staff engineers, one director and one engineering manager (2025). Another poster had 4 interviews scheduled for a staff software role (year not shown). Prep sites disagree on the shape: TechPrep describes 3 to 4 video rounds of 45 to 60 minutes, TechInterview 4 to 6 rounds including one behavioral round, and CleverPrep (ASIC) a half day to a full day. A Taro report dated April 2011 describes four sets of technical rounds on ASIC RTL design basics in Bengaluru followed by a manager interview, and a July 2024 Pune senior software report mentions 5 rounds of programming. Round count varies by business unit, level and region.
Stage 7: Manager and HR rounds (reported for India)
varies
A Taro report from November 2025 describes two technical rounds, one managerial round and one HR discussion in India; an older Bengaluru report (2011) describes a manager round that asked a few technical questions and the candidate's expectations of Broadcom, and a 2008 report lists two technical rounds and one HR round. Hyring, a prep site, lists HR topics as compensation, notice period, location, joining date and documents. Varies by region and level.
Stage 8: Decision and offer
1 to 2 weeks per one prep site; 4 to 8 weeks for the whole process per another; one India candidate reported waiting about a month
CleverPrep (ASIC) says the hiring committee reviews feedback and decides in 1 to 2 weeks; TechInterview describes a hiring committee review and puts the whole process at 4 to 8 weeks; an intern guide gives an average time to hire of about 22 days. A March 2025 Blind post from an India candidate says they interviewed a month earlier and were still waiting. A Blind reply says Broadcom interviews several candidates at once and ranks them by feedback, with the top-ranked candidate getting the offer first (one anecdote); the same thread polled offer timing from 1 week to 7 or more weeks without a visible result. Varies by team, level and region.
Timing figures conflict across sources and rest on prep sites plus a few anecdotes
A tag is the condition given in brackets in the stage name.
Reported interview time, one scale in minutes
Where the minutes go
- Recruiter screen~30 min
- Hiring manager screen45 min
- Technical phone screen45 to 90 min
Not drawn: Application or referral, Assessment or RTL design exercise, Onsite or virtual loop, Manager and HR rounds and Decision and offer, whose durations are not given in minutes.
02 / What Broadcom scores
No publicly documented framework
03 / Coach's notes
Coach's tips.
01
Find out the business unit before you prepare. Broadcom hires by division (Blind posts name CSG, DCSG, Brocade, a PCIe switch group, VCF and others), and the content shifts from RTL and C to virtualization and LeetCode-plus-system-design depending on the group. Recruiters do not always share the loop structure (one Blind poster said theirs did not), so ask directly.
02
Expect your current project to be dissected. One former employee being recruited back reported a director and a lead insisting on details of the present work (2019), and TechPrep says the hiring manager screen probes past projects. A 2011 Bengaluru manager round also asked about the candidate's expectations of Broadcom. Be ready to defend every design choice and number on your resume.
03
For firmware, embedded and networking software roles, drill C fundamentals rather than only LeetCode: pointers, bit manipulation, dry-running code, and classic exercises such as a thread-safe strtok. A Broadcom employee described the work as mostly C-based system design and networking.
04
Train for stamina. Blind posts mention scheduled loops of 5 to 7 hours; the 5 hour senior software loop had three staff engineers, a director and an engineering manager. Plan short, structured answers so the later rounds do not suffer. Early-career routes may be shorter.
05
Plan for a slow close. An India candidate on Blind said in March 2025 they were still waiting a month after interviewing, and a Blind reply says offers go to the top-ranked of several candidates first (one anecdote). Posters also report mixed experiences on negotiation (one in 2023 said they were told Broadcom did not negotiate, another in 2022 said a team director wanted to negotiate numbers), so keep other processes alive until the written offer arrives.
04 / The research
Where this page comes from.
Compiled from public sources across 9 sites. Broadcom's own page is among them: broadcom.com/company/careers.
- sites
- 9
- coaching and prep guides
- 17
- candidate reports and forums
- 12
- Broadcom's own pages
- 2
Source composition
Where the research comes from
Grouped by the kind of site that published each source: Broadcom's own domain, candidate forums, and everything else.
- Coaching and prep guides17
- Candidate reports and forums12
- Broadcom's own pages2
05 / The questions
Reported questions, by category.
Showing questions for
Roles are grouped by the category each question fits, not by the source.
Systems, embedded and networking
7 questions
Explain how a specific networking protocol works under the hood.
Tests depth on a protocol you name, such as state machines, packet formats and failure handling.
Answer questions on the 802.11 (Wi-Fi) specifications.
Tests Wi-Fi MAC and spec knowledge for firmware work; from one 2018 candidate's prep list, not a completed loop.
Compare the I2C, SPI and UART protocols, and discuss RTOS and memory management.
Tests embedded bus trade-offs (wires, speed, addressing) plus RTOS scheduling and memory allocation.
Design a scheduler.
Tests scheduling policy choices such as priority, fairness and preemption, and the data structures behind them.
Design a caching layer.
Tests eviction policy, consistency and invalidation trade-offs when placing a cache in a system.
Explain the difference between cut-through and store-and-forward switching.
Tests the latency versus error-filtering trade-off between switch forwarding modes.
How would you debug a packet loss issue in a high-speed network switch?
Tests systematic fault isolation across buffers, queues, link errors and counters in a switch datapath.
Reported problems, listed so you know what to expect. Practice them in your own editor or on the platform you prefer; SupaCV's practice mode coaches how you talk through them.
Hardware design and verification
8 questions
Explain clock domain crossing techniques for high-speed interfaces.
Tests metastability handling with synchronizers, handshakes and async FIFOs across clock domains.
Explain the trade-offs between synchronous and asynchronous FIFOs.
Tests pointer synchronization, Gray coding, depth sizing and area versus latency.
How would you design a priority-based arbiter for network traffic?
Tests fixed versus round-robin arbitration, starvation avoidance and RTL implementation.
Design a packet buffer manager with credit-based flow control.
Tests buffer allocation, credit accounting and backpressure design for a switch datapath.
How would you debug a timing violation on a critical path?
Tests static timing analysis: reading slack on critical paths, then fixing with pipelining, retiming or sizing.
Implement a CRC calculator optimized for high throughput.
Tests parallel LFSR or XOR-tree CRC logic and the speed versus area trade-off.
How would you approach verifying a complex networking chip?
Tests verification planning: constrained-random stimulus, coverage, scoreboards and reference models.
Implement a deep packet pipeline in SystemVerilog.
Tests pipelining parse, lookup and modify stages within a cycle budget, with stall and bypass handling.
Reported problems, listed so you know what to expect. Practice them in your own editor or on the platform you prefer; SupaCV's practice mode coaches how you talk through them.
Coding and C fundamentals
12 questions
Reverse a linked list.
Tests pointer manipulation and in-place iterative reversal of a singly linked list in O(n) time and O(1) space.
Design an LRU cache.
Tests pairing a hash map with a doubly linked list for O(1) get and put with eviction.
Describe how to find the middle of a linked list in O(n) time with a single traversal.
Tests the slow and fast pointer technique on a linked list in one pass.
Remove the Nth node from the end of a linked list.
Tests the two-pointer gap technique and head-removal edge cases in a single pass.
Implement strtok, then a thread-safe version of it.
Tests C string and pointer handling, the hidden static state in strtok, and making it reentrant with a caller-held save pointer.
Answer bit manipulation questions in C.
Tests bitwise operators, masks and shifts on register-style problems in C.
Answer questions on pointers, arrays, stacks and queues in C.
Tests C pointer semantics and array-backed stack and queue implementation.
Answer very basic C questions and dry-run the code by hand.
Tests tracing C execution by hand, covering pointer, integer and control-flow behavior.
Implement basic data structures in C, such as a linked list, hash table or B-tree.
Tests hand-written C data structures and memory handling; from one 2018 candidate's prep list, not a completed loop.
Explain the difference between stack and heap allocation in C.
Tests memory layout, allocation lifetime and failure modes of stack versus heap in C.
Solve 3Sum.
Tests sorting plus a two-pointer scan to find triplets in O(n^2) while skipping duplicates.
Solve Number of Islands.
Tests grid DFS or BFS flood fill with visited-state tracking on a 2D matrix.
Reported problems, listed so you know what to expect. Practice them in your own editor or on the platform you prefer; SupaCV's practice mode coaches how you talk through them.
Every role
Behavioral and fit
8 questions
Describe the project you are currently working on in detail.
What is the project you are most proud of?
How would you start with the project you will be dealing with during your internship?
Describe a time you could not meet a deadline and how you handled it.
Tell me about a challenging engineering problem you solved. What was your approach?
Describe a time you found and fixed a silicon bug.
How do you handle schedule pressure approaching tape-out?
Why do you want to work at Broadcom?
Your next step
Interviewing at Broadcom?
Make sure your resume gets you to the first round.
Practicing for Broadcom against your resume is in Interview Prep on Career.
Common questions
Quick answers.
How many stages are in Broadcom's interview process?
Broadcom has 8 stages, set out in The process.
Does Broadcom have an official interview framework?
Broadcom has no publicly documented framework, as set out in What Broadcom scores.
What kinds of questions does Broadcom ask?
Broadcom's questions fall into 4 categories, grouped in The questions.
How reliable is this Broadcom interview playbook?
It is compiled from public sources, and the evidence is in The research.
Sources (31)
Every public source this page was compiled from. Links open in a new tab.
9 sites, by sources
- teamblind.com12
- jointaro.com9
- broadcom.com2
- techprep.app2
- cleverprep.com2
- techinterview.org1
- hyring.com1
- extern.com1
- scoutify.com1
- 01broadcom.com/company/careers
- 02broadcom.com/company/careers/culture
- 03techprep.app/blog/broadcom-interview-process
- 04techprep.app/companies/broadcom
- 05cleverprep.com/companies/broadcom
- 06cleverprep.com/companies/broadcom/asic-design-engineer
- 07techinterview.org/companies/broadcom-interview-guide
- 08hyring.com/jobseeker-toolkit/interview-questions/company/broadcom
- 09extern.com/post/broadcom-internship-guide
- 10jointaro.com/interviews/companies/broadcom/work-experiences/softwar…
- 11jointaro.com/interviews/companies/broadcom/work-experiences/staff-e…
- 12jointaro.com/interviews/companies/broadcom/work-experiences/staff-e…
- 13jointaro.com/interviews/companies/broadcom/work-experiences/staff-e…
- 14jointaro.com/interviews/companies/broadcom/experiences/software-eng…
- 15jointaro.com/interviews/companies/broadcom/experiences/software-eng…
- 16jointaro.com/interviews/companies/broadcom/experiences/software-eng…
- 17jointaro.com/interviews/companies/broadcom/experiences/software-eng…
- 18jointaro.com/interviews/companies/broadcom
- 19teamblind.com/post/broadcom-onsite-interview-lh24vpau
- 20teamblind.com/post/broadcom-interview-for-sr-software-engineer-ojgjf…
- 21teamblind.com/post/broadcom-phone-screen-bxnusoaf
- 22teamblind.com/post/broadcom-interview-experience-uwjhsgi2
- 23teamblind.com/post/broadcom-fw-eng-interview-xzyuor4k
- 24teamblind.com/post/how-long-did-it-take-to-receive-an-offer-from-bro…
- 25teamblind.com/company/Broadcom/posts/broadcom-interview
- 26teamblind.com/browse/Broadcom-Interview-73635
- 27teamblind.com/company/Broadcom/posts/broadcom-interview
- 28teamblind.com/company/Broadcom/posts/broadcom-interview
- 29teamblind.com/post/broadcom-ic-design-interview-hme3idu4
- 30teamblind.com/post/broadcom-sta-timing-interview-7p3pk2hd
- 31scoutify.com/companies/broadcom/interview
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How similar companies interview
Compare Broadcom's process with other Hardware, Semiconductors & Aerospace companies in this playbook: